The number of memory miss cycles for instructions in terms of the Instruction count (I) is
Instruction miss cycles = I × 2% × 100 = 2.0 × I
As the frequency of all loads and stores is 20%, we can find the number of memory miss cycles for data references:
Data miss cycles = I × 20% × 5% × 100 = 1.0 × I
The total number of memory-stall cycles is
2.0 I + 1.0 I = 3.0 I
This is three cycles of memory stall per instruction.
Accordingly, the total CPI including memory stalls is
1.5+3.0=4.5.
Since there is no change in instruction count or clock rate, the ratio of the CPU execution times is
CPU time with stalls / CPU time with perfect cache
= ( I×CPIstall×Cycle time ) / ( I×CPIperfect×Cycle time )
= CPIstall / CPIperfect = 4.5 / 1.5
The performance with the perfect cache is better by
4.5/1.5=3.0.