The Forwarding Unit
The following figure shows the forwarding unit in a pipelined datapath.
The unit controls the ALU multiplexors to replace the value from a general-purpose register with the value from the proper pipeline register.
It includes two tasks:
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- Generate two control signals
ForwardA
and ForwardB
, which are used to control the two forwarding multiplexors, and
- Use
Rs
and Rt
in IF/ID and Rw
in ID/EX and EX/MEM.
A Forwarding Example
Consider the following instruction sequence:
lw $4, 100($9) # $4 = Mem[100+[$9]]
add $7, $5, $6 # $7 = $5 + $6
sub $8, $4, $7 # $8 = $4 - $7
When lw
reaches the MEM stage, add
will be in the ALU stage and sub
will be in the Decode stage.
ForwardA =10 ⇒
Forward data from MEM stage and
ForwardB =01 ⇒
Forward ALU result from ALU stage.
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I was just making a suggestion.
Don’t get all bent out of shape (become angry) out it.
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