The power limit has forced a dramatic change in the design of microprocessors. The figure shows the improvement in response time of programs for desktop microprocessors over time.
| Since 2002, the rate has slowed from a factor of 1.5 per year to a factor of only 1.03 per year because of the limits of power, available instruction-level parallelism, and long memory latency. |
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Rather than continuing to decrease the response time of a single program running on the single processor, as of 2006 all desktop and server companies are shipping microprocessors with multiple processors per chip, where the benefit is often more on throughput than on response time.
| Product | AMD Opteron ×4 (Barcelona) | Intel Nehalem | IBM Power 6 | Sun Ultra SPARC T2 (Niagara 2) |
|---|---|---|---|---|
| Cores per chip | 4 | 4 | 2 | 8 |
| Clock rate | 2.5 GHz | ∼ 2.5 GHz ? |
4.7 GHz | 1.4 GHz |
| Microprocessor power | 120 W | ∼ 100 W ? |
∼ 100 W ? |
94 W |
The above table shows the number of cores per chip, clock rate, and power for 2008 multicore microprocessors. Today, for programmers to get significant improvement in response time, they need to rewrite their programs to take advantage of multiple processors.