Cache Basics Review II

For a direct-mapped cache design with 32-bit address, the following bits of the address are used to access the cache: (i) tag: 31–10, (ii) index: 9–4, and (iii) offset: 3–0. Answer the following questions:


  The cache block size = words      
  The number of the cache entries =      

Starting from power on, the byte-addressed cache references are recorded:

# Address Address in Binary Cache Index (H)it/(M)iss Replace (Y/N)
1 0 ... 0000 0000 00002 0 M N
2 4 ... 0000 0000 01002
3 16 ... 0000 0001 00002
4 132 ... 0000 1000 01002
5 232 ... 0000 1110 10002
6 160 ... 0000 1010 00002
7 1024 ... 0100 0000 00002
8 30 ... 0000 0001 11102
9 140 ... 0000 1000 11002
10 3100 ... 1100 0001 11002
11 180 ... 0000 1011 01002
12 2180 ... 1000 1000 01002


  The number of blocks are replaced =      
  The hit ratio =      




      I do not think a recession is in the cards (likely) this year.    
      Consumer confidence is very strong