RAW Hazard Detection (Cont.)

Another example of RAW (Read After Write) data hazard is as follows: 
   i3.  add   $2,  $1, $3     # $2  = $1 + $3
   i4.  and   $12, $4, $5     # $12 = $4 ∧ $5
   i5.  or    $13, $6, $2     # $13 = $6 ∨ $2
RAW data hazards could happen at both EX and MEM stages.

MEM Hazard
This kind of hazards requires forwarding for operations that use results during the MEM stage. It occurs when

  • The current instruction being decoded is in the ID stage and the source register is in the IF/ID register and

  • The second prior instruction is in the MEM stage and the destination register is in the EX/MEM register.

Therefore, a pair of hazard conditions are as follows: 
   2a.  IF/ID.Rs = EX/MEM.Rw
   2b.  IF/ID.Rt = EX/MEM.Rw
where “EX/MEM.Rw” refers to the Rw register whose value is found in the pipeline register EX/MEM.

Hazard of the above instruction sequence can be detected by Condition 2b.