The following figure shows the hardware necessary to support forwarding for operations that use results during the EX and MEM stages. Two multiplexors are added at the inputs of A and B registers in the ID/EX pipeline register and two kinds of data are forwarded:
- ALU output in the EX stage and
- ALU result or load data in the MEM stage.
ForwardA and ForwardB, control forwarding.
They are generated by a forwarding unit in the ID stage.
| The top figure is the pipelined datapath without forwarding and the bottom one is the datapath with forwarding hardware including two extra multiplexors and two more control signals. |
↑ No forwarding ⇓ ↓ With forwarding 
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