Control Hazards

Control hazards are defined as follows:
Control hazards, also called branch hazards, occur when the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed.
Branch instructions can cause great performance loss if they are not handled accordingly. Two issues related to branch instructions are Branch instruction is decoded in the ID stage at which a new instruction is already being fetched. The following example is from a previous slide. The control hazard can be handled by stalling, which is similar to the one used in the data hazards. The stalling causes 2-cycle branch delay because Therefore, the next instruction after the branch is known after the EX stage of the branch instruction and is fetched at the MEM stage that is 2-cycle late. One bubble (nop) is inserted into clock cycle 3 and the next instruction is re-fetched at clock cycle 4.

Clock cycle
1 2 3 4 5 6 7 8 9
Branch
 IF ID EX MEM WB        
Branch successor
   IF (stall) stall IF ID EX MEM WB  
Branch successor+1
         IF ID EX MEM WB




      “I will no longer mutilate and destroy myself    
      in order to find a secret behind the ruins.”    
      ― Hermann Hesse, Siddhartha