Control Signals (Cont.)

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For a pipelined datapath, the control lines are divided into five groups according to the pipeline stage. The control signals are pipelined as the instruction moves by extending the pipeline registers to include the control signals. Each stage uses some of the control signals.

Instruction Fetch (IF)

The control signals to read instruction memory and to write the PC are always asserted, so there is nothing special to control in this stage.

Instruction Decode/Register File Read (ID)

This stage generates all the control signals. RegDst, for the result register, is used in this stage.

Execution/Address Calculation (EX)

The signals to be set include

• ALUOp, an ALU operation (instead of using the opcode, the ALU control uses the control signal ALUOp sent from the main control),
• ALUSrc, which picks BusB or sign-extended immediate for the ALU, and
• Beq, Bne, and J, which are for the “Next PC” logic.

Memory Access (MEM)

The control lines set in this stage include

• MemRead, which is for the load instructions,
• MemWrite, which is for the store instructions, and
• MemtoReg, which decides between sending the ALU result or the memory value to the register file.

Recall that PCSrc selects the next sequential address unless control asserts branch and the ALU result was 0.

Write-Back (WB)

The control line is RegWrite, which writes the chosen value.