Slide 13.8: Control signals

Control Signals

Just as we added control to the single-cycle datapath previously, the following figure shows the pipelined datapath with the control signals.

The control signal values are similar to the ones of the single-cycle datapath.

Op	Decode Signal	Execute Stage Control Signals					Memory Stage Control Signals			Writeback Signal
Op	`RegDst`	`ALUSrc`	`ALUOp`	`Beq`	`Bne`	`J`	`MemRead`	`MemWrite`	`MemtoReg`	`RegWrite`
R-type			R-Type
`addi`	0 (`rt`)	1 (Imm)	ADD	0	0	0	0	0	0	1
`slti`	0 (`rt`)	1 (Imm)	SLT	0	0	0	0	0	0	1
`andi`	0 (`rt`)	1 (Imm)	AND	0	0	0	0	0	0	1
`ori`	0 (`rt`)	1 (Imm)	OR	0	0	0	0	0	0	1
`lw`
`sw`	x	1 (Imm)	ADD	0	0	0	0	1	x	0
`beq`
`bne`	x	0 (Reg)	SUB	0	1	0	0	0	x	0
`j`	x	x	x	0	0	1	0	0	x	0