The previous figure suggests that three instructions need three datapaths. Instead, registers are added to hold data so that portions of a single datapath can be shared during instruction execution. For example, the instruction memory is used during only one of the five stages of an instruction, allowing it to be shared by following instructions during the other four stages.
To retain the value of an individual instruction for its other four stages, the value read from instruction memory must be saved in a register.Similar arguments apply to every pipeline stage. The following figure shows the pipelined datapath with the pipeline registers. All instructions advance during each clock cycle from one pipeline register to the next.
The pipeline registers are labeled by the stages that they separate; e.g., the first is labeled IF/ID because it separates the instruction fetch and instruction decode stages. The registers must be wide enough to store all the data corresponding to the lines that go through them. For example, the IF/ID register must be 64 bits wide, because it must hold both the 32-bit instruction fetched from memory and the incremented 32-bit PC address.