MIPS Instruction Execution Steps
The same principles of pipelining can apply to MIPS processors where we pipeline instruction execution.
MIPS instructions classically take five steps:
- Fetch instruction from memory.
- Read registers while decoding the instruction.
The regular format of MIPS instructions allows reading and decoding to occur simultaneously.
- Execute the operation or calculate an address.
- Access an operand in data memory.
- Write the result into a register.
For example, the table shows the total time for each instruction calculated from the time for each component.
This calculation assumes that the multiplexors, control unit, PC accesses, and sign extension unit have no delay.
| Instruction class |
Instruction fetch |
Register read |
ALU operation |
Data access |
Register write |
Total time |
Load word (lw) |
200 ps |
100 ps |
200 ps |
200 ps |
100 ps |
800 ps |
Store word (sw) |
200 ps |
100 ps |
200 ps |
200 ps |
— |
700 ps |
R-format (add, sub, AND, OR, slt) |
200 ps |
100 ps |
200 ps |
— |
100 ps |
600 ps |
Branch (beq) |
200 ps |
100 ps |
200 ps |
— |
— |
500 ps |
The operation times for the major functional units in this table are
- 200 ps (1 ps = 10-12 second) for memory access,
- 200 ps for ALU operation, and
- 100 ps for register file read or write.
The discussion only focuses on eight instructions: load word (
lw), store word (
sw), add (
add), subtract (
sub), AND (
and), OR (
or), set less than (
slt), and branch on equal (
beq).