Pipelined Control

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Implementing control means setting the control lines to appropriate values in each stage for each instruction. The figure shows the previous pipelined datapath with the control signals connected to the control portions of the pipeline registers.


The control values for the last three stages are created during the instruction decode (ID) stage and then placed in the ID/EX pipeline register where

• EX, which is used by the EX stage and includes ALUSrc, ALUOp, J, Beq, and Bne,
• M, which is used by the MEM stage and includes MemRead, MemWrite, and MemtoReg, and
• WB, which is used by the WB stage and includes RegWrite.

The control lines for each pipe stage are used, and remaining control lines are then passed to the next pipeline stage.