RISC is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles.
| Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as “free and open” because its specifications are released under permissive open-source licenses and can be implemented without paying royalties. |
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RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981.
| At its core, an instruction set architecture defines the interface between software and hardware, dictating how a processor executes instructions. RISC-V follows the principles of RISC, emphasizing simplicity and efficiency in instruction execution. Some commands of RISC-V are given on the right. |
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“If you think you are too small to make a difference, try sleeping with a mosquito.” ― Dalai Lama |